Exceptional Hardware and Software Meeting 2014
pushing frontiers of open source & DIY
DESY Hamburg site, June 27-29 2014
Yosys is the first full-featured open source software for Verilog HDL synthesis. It supports most of Verilog-2005 and is well tested with real-world designs from the ASIC and FPGA world.
Learn how to use Yosys to create your own custom synthesis flow and discover why open source HDL synthesis is important for researchers, hobbyists, educators and engineers alike.
The presentation covers basic concepts of Yosys and writing simple synthesis scripts. There will be also a workshop covering advanced topics.
Yosys is the first step towards a fully open FPGA/ASIC toolchain, and is currently used with vendor place-and-route tools.